FAIL – All configured tests were completed with at least one error was detected or MAXERRCOUNT is exceeded at any point of the test.PASS – All configured tests were completed without any errors detected.Revised criteria for determining the final result of a memory test Added preliminary support for Ryzen Zen 4 DDR5 chip decoding.Fixed error in saving report files due to invalid characters in the file name.Fixed sending corrupted TCP status XML data to management console.Fixed TCP connection to management console being refused for certain Apache configurations.Fixed DIMM error count reporting for 2-slot motherboards.Fixed text being truncated in DIMM results screen.Fixed inconsistent slot name in DIMM results screen.Fixed display of negative RAM temperatures.Fixed display of negative CPU temperatures.Fixed disabling of hyperthreads for CPUs with hybrid cores.Extended DIMM decoding support for additional Alder Lake and Raptor Lake chipset variants.Added DIMM temperature support for Intel Broxton chipsets.Added ECC support for Intel Raptor Lake chipsets.Fixed crash when running the Block Test RAM benchmark.Reduced the execution time of hammer test by reducing the maximum number of memory segments to hammer from 64 to 32.Reduced the execution time of hammer test by increase minimum segment size per thread from 128MB to 512MB.Changed units from MHz to MT/s when referring to DRAM transfer rate (typically double the clock speed for DDR RAM).Include list of all supported SPD profiles (eg.Previously, static memory parameters from SPD/SMBIOS were displayed which were not necessarily the actual configured parameters. Display configured RAM settings in test screen.Added support for displaying and reporting DDR5 XMP 3.0 SPD profiles.If more than 1 configurations are found, the user is prompted to select a configuration Added support for multiple configurations in a single configuration file.This includes clock speed, timings, channel mode and voltages. Added support for displaying and reporting configured RAM settings for supported chipsets.
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